Display panel

ABSTRACT

A display panel includes a substrate including a display area and a middle area, wherein an opening is defined in the substrate, the display area surrounds the opening, and the middle area is disposed between the opening and the display area; a light-emitting device in the display area, including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; an encapsulation layer covering the light-emitting device, and including at least one inorganic encapsulation layer; a first groove in the middle area on the substrate; and a second groove in the middle area, having an undercut shape that is concave in a thickness direction of a multi-layered film in the substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119to Korean Patent Application No. 10-2020-0188060, filed on Dec. 30,2020, in the Korean Intellectual Property Office, the disclosure ofwhich is incorporated by reference herein in its entirety.

BACKGROUND 1. Field

One or more embodiments of the disclosure relate to a display panel, andmore particularly, to a display panel including an opening area.

2. Description of the Related Art

Display apparatuses have been used for various purposes. In addition,because the thickness and weight of the display apparatuses have beenreduced, the utilization range of the display apparatuses has increased.

In a display apparatus, various functions added to or linked to adisplay apparatus are being added while increasing a display area. As amethod of adding various functions while increasing an area, researchinto a display apparatus having an area for providing other variousfunctions than an image display in a display area has been continuouslyconducted.

SUMMARY

However, in a display panel according to the related art, defects causedby moisture infiltration may occur.

One or more embodiments include a display panel having an improvedmoisture permeability prevention performance. However, the abovetechnical features are exemplary, and the scope of the disclosure is notlimited thereto.

Additional aspects will be set forth in part in the description whichfollows and, in part, will be apparent from the description, or may belearned by practice of the presented embodiments of the disclosure.

According to an embodiment, a display panel includes a substrateincluding an opening, a display area surrounding the opening, and amiddle area between the opening and the display area, a light-emittingdevice in the display area, the light-emitting device including a pixelelectrode, an opposite electrode, and an intermediate layer between thepixel electrode and the opposite electrode, an encapsulation layercovering the light-emitting device, the encapsulation layer including atleast one inorganic encapsulation layer, a first groove in the middlearea, the first groove being on the substrate, and a second groove inthe middle area, the second groove having an undercut shape that isconcave in a thickness direction of a multi-layered film in thesubstrate.

The first groove may include a 1-1st hole in an inorganic insulatinglayer on the substrate and a 1-2nd hole in an organic insulating layeron the inorganic insulating layer, wherein the 1-2nd hole may beconnected to the 1-1st hole.

The first groove may include a first tip that is a protrusion from ametal pattern layer on the organic insulating layer toward a center ofthe first groove.

An organic material layer included in the intermediate layer or theopposite electrode may be disconnected by the first tip.

The at least one inorganic encapsulation layer may continuously cover aninner surface and a lower surface of the metal pattern layer and aninner surface of the organic insulating layer.

The first tip may have a multi-layered structure, in which a firstlayer, a second layer, and a third layer are sequentially stacked, and aconcave portion that is obtained by denting the second layer in adirection away from the center of the first groove, and the organicmaterial layer included in the intermediate layer or the oppositeelectrode may be disconnected by the multi-layered structure.

The display panel may include a lower layer under the first groove, thelower layer having an upper surface corresponding to a bottom surface ofthe first groove.

The display panel may further include metal dummy stacks at oppositesides of the first groove based on a line that passes through the centerof the first groove and is perpendicular to an upper surface of thesubstrate, the metal dummy stacks may each include one or more metallayers stacked with an insulating layer therebetween.

The multi-layered film included in the substrate may include a baselayer and a barrier layer on the base layer.

The second groove may include a 2-1st hole or a 2-1st recess in the baselayer, and a 2-2nd hole in the barrier layer, and the 2-2nd hole may beconnected to the 2-1st hole or the 2-1st recess.

The second groove may include a second tip that is a protrusion from thebarrier layer toward a center of the second groove.

An organic material layer included in the intermediate layer or theopposite electrode may be disconnected by the second tip.

The at least one inorganic encapsulation layer may continuously cover aninner surface and a lower surface of the barrier layer and an innersurface of the base layer.

The display panel may further include a disconnection portion in themiddle area, the disconnection portion having at least one of a firststack structure, in which a 1-1st sub-layer, a 1-2nd sub-layer, and a1-3rd sub-layer are sequentially stacked, and a second stack structureon the first stack structure, the second stack structure including a2-1st sub-layer, a 2-2nd sub-layer, and a 2-3rd sub-layer sequentiallystacked, wherein an organic material layer included in the intermediatelayer or the opposite electrode may be disconnected by the disconnectionportion.

The first stack structure may have a first concave portion formed bydenting the 1-2nd sub-layer toward a center thereof, and the secondstack structure may have a second concave portion formed by denting the2-2nd sub-layer toward a center thereof.

The display panel may include a thin film transistor on the substrate,the thin film transistor including a semiconductor layer, a gateelectrode overlapping the semiconductor layer, and a source electrodeand a drain electrode electrically connected to the semiconductor layer,wherein each of the source electrode and the drain electrode may have astructure, in which a layer having a material same as a material in the1-1st sub-layer, a layer having a material same as a material in the1-2nd sub-layer, and a layer having a material same as a material in the1-3rd sub-layer are sequentially stacked.

The display panel may further include a contact metal layer on the thinfilm transistor, the contact metal layer being electrically connected tothe source electrode or the drain electrode, wherein the contact metallayer has a structure, in which a layer having a material same as amaterial in the 2-1st sub-layer, a layer having a material same as amaterial in the 2-2nd sub-layer, and a layer having a material same as amaterial in the 2-3rd sub-layer may be sequentially stacked.

The disconnection portion may further include a third stack structure onthe second stack structure, the third stack structure including a 3-1stsub-layer, a 3-2nd sub-layer, and 3-3rd sub-layer sequentially stacked.

The first stack structure may have a first concave portion formed bydenting the 1-2nd sub-layer toward a center thereof, the second stackstructure may have a second concave portion formed by denting the 2-2ndsub-layer toward a center thereof, and the third stack structure mayhave a third concave portion formed by denting the 3-2nd sub-layertoward a center thereof.

The pixel electrode may have a structure, in which a layer having amaterial same as a material in the 3-1st sub-layer, a layer having amaterial same as a material in the 3-2nd sub-layer, and a layer having amaterial same as a material in the 3-3rd sub-layer may be sequentiallystacked.

Other aspects, features and advantages of the disclosure will becomebetter understood through the accompanying drawings, the claims and thedetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and advantages of certainembodiments of the disclosure will be more apparent from the followingdescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a perspective view showing a region of a display apparatusaccording to an embodiment;

FIG. 2 is a cross-sectional view showing a region of the displayapparatus of FIG. 1;

FIG. 3 is a plan view partially showing a region of a display panelaccording to an embodiment;

FIG. 4 is an equivalent circuit diagram of one pixel in a display panelaccording to an embodiment;

FIG. 5 is a plan view partially showing a region of a display panelaccording to an embodiment;

FIG. 6 is a cross-sectional view showing a region of a display panelaccording to an embodiment;

FIG. 7 is a cross-sectional view showing a region of a display panelaccording to an embodiment;

FIGS. 8, 9, and 10 are cross-sectional views sequentially showing someof processes of manufacturing the display panel of FIG. 7;

FIG. 11 is a cross-sectional view showing a region of a display panelaccording to an embodiment;

FIGS. 12, 13, and 14 are cross-sectional views sequentially showing someof processes of manufacturing the display panel of FIG. 11;

FIG. 15 is a plan view partially showing a region of a display panelaccording to an embodiment;

FIG. 16 is a cross-sectional view showing a region of a display panelaccording to an embodiment;

FIG. 17 is a cross-sectional view partially showing a disconnectionportion according to an embodiment;

FIG. 18A is a cross-sectional view partially showing a disconnectionportion according to another embodiment;

FIG. 18B is a cross-sectional view partially showing a disconnectionportion according to another embodiment;

FIG. 19 is a cross-sectional view partially showing a disconnectionportion according to another embodiment;

FIG. 20 is a cross-sectional view partially showing a disconnectionportion according to another embodiment;

FIG. 21 is a cross-sectional view partially showing a disconnectionportion according to another embodiment;

FIG. 22 is a cross-sectional view partially showing a disconnectionportion according to another embodiment.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of whichare illustrated in the accompanying drawings, wherein like referencenumerals refer to like elements throughout. In this regard, the presentembodiments may have different forms and should not be construed asbeing limited to the descriptions set forth herein. Accordingly, theembodiments are merely described below, by referring to the figures, toexplain aspects of the present description. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items. Throughout the disclosure, the expression “atleast one of a, b or c” indicates only a, only b, only c, both a and b,both a and c, both b and c, all of a, b, and c, or variations thereof.

As the present disclosure allows for various changes and numerousembodiments, particular embodiments will be illustrated in the drawingsand described in detail in the written description. The attacheddrawings for illustrating one or more embodiments are referred to inorder to gain a sufficient understanding, the merits thereof, and theobjectives accomplished by the implementation. However, the embodimentsmay have different forms and should not be construed as being limited tothe descriptions set forth herein.

While such terms as “first,” “second,” etc., may be used to describevarious components, such components are not be limited to the aboveterms. The above terms are used only to distinguish one component fromanother.

An expression used in the singular encompasses the expression of theplural, unless it has a clearly different meaning in the context.

In the present specification, it is to be understood that the terms“including,” “having,” and “comprising” are intended to indicate theexistence of the features, numbers, steps, actions, components, parts,or combinations thereof disclosed in the specification, and are notintended to preclude the possibility that one or more other features,numbers, steps, actions, components, parts, or combinations thereof mayexist or may be added.

It will be understood that when a layer, region, or component isreferred to as being “formed on” another layer, region, or component, itmay be directly or indirectly formed on the other layer, region, orcomponent. That is, for example, intervening layers, regions, orcomponents may be present.

Sizes of components in the drawings may be exaggerated for convenienceof explanation. In other words, since sizes and thicknesses ofcomponents in the drawings are arbitrarily illustrated for convenienceof explanation, the following embodiments are not limited thereto.

When a certain embodiment may be implemented differently, a specificprocess order may be performed differently from the described order. Forexample, two consecutively described processes may be performedsubstantially at the same time or performed in an order opposite to thedescribed order.

In the specification, the phrase “A and/or B” denotes A, B, or A and B.In addition, the phrase “at least one of A and B” denotes A, B, or A andB.

In the embodiments below, when layers, areas, or elements or the likeare referred to as being “connected,” it will be understood that theymay be directly connected or an intervening portion may be presentbetween layers, areas or elements. For example, when layers, areas, orelements or the like are referred to as being “electrically connected,”they may be directly electrically connected, or layers, areas orelements may be indirectly electrically connected and an interveningportion may be present.

The x-axis, the y-axis and the z-axis are not limited to three axes ofthe rectangular coordinate system, and may be interpreted in a broadersense. For example, the x-axis, the y-axis, and the z-axis may beperpendicular to one another, or may represent different directions thatare not perpendicular to one another.

The embodiments will be described below in more detail with reference tothe accompanying drawings. Those components that are the same or are incorrespondence are rendered the same reference numeral regardless of thefigure number, and redundant explanations are omitted.

FIG. 1 is a perspective view showing a region of a display apparatus 1according to an embodiment.

Referring to FIG. 1, the display apparatus 1 according to an embodimentmay include an opening area OA (or first area) and a display area DA (orsecond area) surrounding the opening area OA. A plurality of pixels maybe in the display area DA, and the display area DA may display imagesvia the pixels. The opening area OA may be entirely surrounded by thedisplay area DA.

A middle area MA (or third area) may be between the opening area OA andthe display area DA. The middle area MA is a non-display area in whichthe pixels are not provided, and may include wirings detouring theopening area OA. A peripheral area PA (or fourth area) surrounding thedisplay area DA may be also a non-display area in which the pixels arenot provided like the middle area MA, and various kinds of wirings andinternal circuits may be in the peripheral area PA.

In FIG. 1, the opening area OA is at a center portion of the displayarea DA in a width direction (e.g., x-direction) of the displayapparatus 1, but in another embodiment, the opening area OA may beoffset to left or right side in the width direction of the displayapparatus 1. Alternatively, the opening area OA may be at variouslocations, e.g., an upper side, an intermediate side, or a lower side ina lengthwise direction (e.g., y-direction) of the display apparatus 1.

FIG. 1 shows the display apparatus 1 includes one opening area OA, butin another embodiment, the display apparatus 1 may include a pluralityof opening areas OA.

FIG. 2 is a cross-sectional view showing a region of the displayapparatus 1 of FIG. 1. FIG. 2 is a cross-sectional view of the displayapparatus 1 taken along line I-I′ of FIG. 1.

Referring to FIG. 2, the display apparatus 1 may include a display panel10 and a component 70 provided in the opening area OA of the displaypanel 10. In an embodiment, the display panel 10 and the component 70may be accommodated in a housing HS. In another embodiment, the housingHS may be omitted.

The display panel 10 may include a display element layer 20, an inputsensing layer 40, an optical functional layer 50, and a cover window 60.

The display element layer 20 may include display elements emitting lightfor displaying images. The display element may include a light-emittingdevice. In an embodiment, the light-emitting device may include anorganic light-emitting diode including an organic emission layer. Inanother embodiment, the light-emitting device may include an inorganiclight-emitting diode including an inorganic material. The inorganiclight-emitting diode may include a PN diode including inorganic materialsemiconductor-based materials. In another embodiment, the light-emittingdevice may include quantum dots as an emission layer. Hereinafter, forconvenience of description, a case in which the light-emitting deviceincludes an organic light-emitting diode will be described below.

The input sensing layer 40 may obtain coordinate information generatedaccording to an external input, e.g., a touch event. The input sensinglayer 40 may include a sensing electrode and trace lines connected tothe sensing electrode. The input sensing layer 40 may be on the displayelement layer 20. The input sensing layer 40 may sense an external inputby a mutual capacitance method and/or a self-capacitance method, but isnot limited thereto.

The input sensing layer 40 may be directly on the display element layer20 or may be separately manufactured and then coupled to the displayelement layer 20 via an adhesive layer such as an optically clearadhesive. For example, the input sensing layer 40 may be obtainedsuccessively after the process of arranging the display element layer20. In another embodiment, the adhesive layer between the input sensinglayer 40 and the display element layer 20 may be omitted. FIG. 2 showsthat the input sensing layer 40 is between the display element layer 20and the optical functional layer 50, but in another embodiment, theinput sensing layer 40 may be on the optical functional layer 50.

The optical functional layer 50 may include an anti-reflection layer.The anti-reflection layer may reduce a reflectivity of light incident tothe display panel 10 from outside (external light) via the cover window60. The anti-reflection layer may include a retarder and a polarizer. Inanother embodiment, the anti-reflection layer may include a black matrixand color filters. The color filters may be arranged taking into accounta color of light emitted from each of the light-emitting devices in thedisplay element layer 20.

In order to improve a transmittance of the opening area OA, an opening10OP that penetrates through some of layers of the display panel 10 isdefined in the display panel 10. The opening 10OP may include first,second, and third openings 20OP, 40OP, and 50OP that respectivelypenetrate through the display element layer 20, the input sensing layer40, and the optical functional layer 50. That is, the first opening 20OPis defined in the display element layer 20, the second opening 40OP isdefined in the input sensing layer 40, and the third opening 50OP isdefined in the optical functional layer 50. The first opening 20OP ofthe display element layer 20, the second opening 40OP of the inputsensing layer 40, and the third opening 50OP of the optical functionallayer 50 may overlap one another and configure one opening 10OP of thedisplay panel 10.

The cover window 60 may be disposed on the optical functional layer 50.The cover window 60 may be coupled to the optical functional layer 50via an adhesive layer such as an optical clear adhesive (OCA) providedbetween the cover window 60 and the optical functional layer 50. Thecover window 60 may include a glass material.

The opening area OA may be a kind of component area (e.g., a sensorregion, a camera region, a speaker region, etc.) in which the component70 for adding various functions to the display apparatus 1 is located.That is, the component 70 overlaps the opening area OA.

The component 70 may include an electronic element. For example, thecomponent 70 may include an electronic element using light or sound. Forexample, the electronic element may include a sensor using light such asan IR sensor, a camera capturing an image by receiving light, a sensorfor outputting and sensing light or sound to measure a distance orrecognize a fingerprint, a small-sized lamp illuminating light, aspeaker for outputting sound, etc. The electronic element using lightmay use light of various wavelength bands such as visible light,infrared rays, ultraviolet rays, etc. The opening area OA may correspondto a transmission area through which light and/or sound output from thecomponent 70 or proceeding towards the component 70 may pass from theoutside.

FIG. 3 is a plan view partially showing a region of the display panel 10according to an embodiment.

Referring to FIG. 3, the display panel 10 may include the opening areaOA, the display area DA, the middle area MA, and the peripheral area PA.

The display panel 10 may include a plurality of pixels P in the displayarea DA, and may display images by using light emitted from each of thepixels P. Each of the pixels P may emit red light, green light, or bluelight. The light-emitting device of each pixel may be electricallyconnected to a scan line SL and a data line DL.

The peripheral area PA may include a scan driver 2100 for providing eachpixel P with a scan signal, a data driver 2200 for providing each pixelP with a data signal, and a main power line (not shown) and a secondmain power line (not shown) for supplying first and second powervoltages. The scan drivers 2100 may be disposed at opposite sides withrespect to the display area DA. In this case, the pixels P at a leftside of the opening area OA may be connected to the scan driver 2100 atthe left side, and the pixels P at a right side of the opening area OAmay be connected to the scan driver 2100 at the right side.

The middle area MA may surround the opening area OA. The middle area MAis an area in which the display element such as a light-emitting deviceemitting light is not arranged, and signal lines providing signals tothe pixels P around the first area OA may pass through the middle areaMA. For example, the data lines DL and/or the scan lines SL cross thedisplay area DA, and some of the data lines DL and/or the scan lines SLmay detour an edge of the opening area OA of the display panel 10, whichis provided in the opening area OA, in the middle area MA. In anembodiment, FIG. 3 shows that the data lines DL cross the display areaDA in the y-direction, and some of the data lines DL detour so as topartially surround the opening area OA in the middle area MA. The scanlines SL cross the display area DA in the x-direction, and may be spacedapart from one another with the opening area OA therebetween.

FIG. 3 shows that the data driver 2200 is adjacent to one side of thesubstrate 100, but in another embodiment, the data driver 2200 may be ona printed circuit board that is electrically connected to a pad at oneside of the display panel 10. The circuit board may be flexible, and maybe partially curved to be under the rear surface of the substrate 100.

FIG. 4 is an equivalent circuit diagram of one pixel in the displaypanel according to an embodiment.

Referring to FIG. 4, the pixel P described above with reference to FIG.3 may emit light through a light-emitting device LED, and thelight-emitting device may be electrically connected to a pixel circuitPC.

Also, the pixel circuit PC may include a first thin film transistor T1,a second thin film transistor T2, a third thin film transistor T3, afourth thin film transistor T4, a fifth thin film transistor T5, a sixththin film transistor T6, a seventh thin film transistor T7, and astorage capacitor Cst.

The second thin film transistor T2 is a switching thin film transistorand is connected to a scan line SL and a data line DL, and may beconfigured to transfer a data voltage (or data signal Dm) input from thedata line DL to the first thin film transistor T1 based on a switchingvoltage (or switching signal Sn) input from the scan line SL. Thestorage capacitor Cst is connected to the second thin film transistor T2and a driving voltage line PL and may store a voltage corresponding to adifference between a voltage transferred from the second thin filmtransistor T2 and a first power voltage ELVDD supplied to the drivingvoltage line PL.

The first thin film transistor T1 is a driving thin film transistorconnected to the driving voltage line PL and the storage capacitor Cstand may control a driving current flowing in the light-emitting deviceLED from the driving voltage line PL, corresponding to the voltage valuestored in the storage capacitor Cst. The light-emitting device LED mayemit light having a predetermined luminance according to the drivingcurrent. An opposite electrode (e.g., a cathode) of the light-emittingdevice LED may receive supply of a second power voltage ELVSS.

The third thin film transistor T3 is a compensation thin film transistorand a gate electrode of the third thin film transistor T3 may beconnected to the scan line SL. A source electrode (or drain electrode)of the third thin film transistor T3 may be connected to a drainelectrode (or source electrode) of the first thin film transistor T1 andmay be also connected to a pixel electrode of the light-emitting deviceLED via the sixth thin film transistor T6. The drain electrode (orsource electrode) of the third thin film transistor T3 may be connectedto one electrode of the storage capacitor Cst, the source electrode (ordrain electrode) of the fourth thin film transistor T4 and the gateelectrode of the first thin film transistor T1. The third thin filmtransistor T3 is turned on according to the scan signal Sn transferredthrough the scan line SL, and connects the gate electrode and the drainelectrode of the first thin film transistor T1 to each other fordiode-connecting the first thin film transistor T1.

The fourth thin film transistor T4 is an initialization thin filmtransistor, and a gate electrode of the fourth thin film transistor T4may be connected to a previous scan line SL−1. The drain electrode (orsource electrode) of the fourth thin film transistor T4 may be connectedto the initialization voltage line VL. The source electrode (or drainelectrode) of the fourth thin film transistor T4 may be connected to oneelectrode of the storage capacitor Cst, the drain electrode (or sourceelectrode) of the third thin film transistor T3, and the gate electrodeof the first thin film transistor T1. The fourth thin film transistor T4is turned on according to a previous scan signal Sn-1 transferredthrough the previous scan line SL-1 to transfer an initializationvoltage Vint to the gate electrode of the first thin film transistor T1and perform an initialization operation for initializing a voltage atthe gate electrode of the first thin film transistor T1.

The fifth thin film transistor T5 is an operation control thin filmtransistor, and a gate electrode thereof may be connected to an emissioncontrol line EL. The source electrode (or drain electrode) of the fifththin film transistor T5 may be connected to the driving voltage line PL.The drain electrode (or source electrode) of the fifth thin filmtransistor T5 is connected to the source electrode (or drain electrode)of the first thin film transistor T1 or the drain electrode (or sourceelectrode) of the second thin film transistor T2.

The sixth thin film transistor T6 is an emission control thin filmtransistor, and a gate electrode thereof may be connected to theemission control line EL. The source electrode (or drain electrode) ofthe sixth thin film transistor T6 may be connected to the drainelectrode (or source electrode) of the first thin film transistor T1 andthe source electrode (or drain electrode) of the third thin filmtransistor T3. The drain electrode (or source electrode) of the sixththin film transistor T6 may be electrically connected to the pixelelectrode of the light-emitting device LED. The fifth thin filmtransistor T5 and the sixth thin film transistor T6 are simultaneouslyturned on according to an emission control signal En transferred throughthe emission control line EL to transfer the driving voltage ELVDD tothe light-emitting device LED, and a driving current flows through thelight-emitting device LED.

The seventh thin film transistor T7 may be an initialization thin filmtransistor that initializes the pixel electrode of the light-emittingdevice LED. A gate electrode of the seventh thin film transistor T7 maybe connected to a post scan line SL+1. A source electrode (or drainelectrode) of the seventh thin film transistor T7 may be connected tothe pixel electrode of the light-emitting device LED. The drainelectrode (or source electrode) of the seventh thin film transistor T7may be connected to the initialization voltage line VL. The sevenththin-film transistor T7 is turned on according to a post scan signalSn+1 transferred through the post scan line SL+1 to initialize the pixelelectrode of the light-emitting device LED.

In FIG. 4, the fourth thin film transistor T4 and the seventh thin filmtransistor T7 are respectively connected to the previous scan line SL−1and the post scan line SL+1, but in another embodiment, the fourth thinfilm transistor T4 and the seventh thin film transistor T7 may beconnected to the previous scan line SLn−1 to operate according to aprevious scan signal Sn−1.

Another electrode of the storage capacitor Cst may be connected to thedriving voltage line PL. One electrode of the storage capacitor Cst maybe connected to the gate electrode of the first thin film transistor T1,the drain electrode (or source electrode) of the third thin filmtransistor T3, and the source electrode (or drain electrode) of thefourth thin film transistor T4.

An opposite electrode (e.g., a cathode) of the light-emitting device LEDmay receive a supply of the common voltage ELVSS. The light-emittingdevice LED emits light after receiving a driving current from the firstthin film transistor T1.

FIG. 5 is a plan view partially showing a region of a display panelaccording to an embodiment.

Referring to FIG. 5, the pixels P are in the display area DA. The middlearea MA may be between the opening area OA and the display area DA. Asdescribed above with reference to FIGS. 3 and 4, each of the pixels Pincludes the light-emitting device and may emit red light, green light,or blue light emitted from the light-emitting device to outside.

From among the signal lines supplying signals to the pixel circuitconnected to the light-emitting device of each pixel P, signal linesadjacent to the opening area OA may detour the opening area OA and/orthe opening 10OP. Some of the data lines DL passing through the displayarea DA extend in the y-direction to provide data signals to the pixelsP arranged above and under the opening area OA, and may detour along anedge of the opening area OA and/or the opening 10OP in the middle areaMA.

A bypass portion DL-C1 of at least one data line DL from among the datalines DL may be at a different layer from an extending portion DL-L1crossing the display area DA, and the bypass portion DL-C1 and theextending portion DL-L1 of the data line DL may be connected to eachother via a contact hole CNT. A bypass portion DL-C2 of at least one ofthe data lines DL may be at the same layer as that of an extendingportion DL-L2, and may be integrally formed with the extending portionDL-L2.

The scan line SL may be isolated or disconnected about the opening areaOA. The scan line SL at the left side of the opening area OA may receivea signal from the scan driver 2100 at the left side of the display areaDA as described above with reference to FIG. 3, and the scan line SL atthe right side of the opening area OA may receive a signal from the scandriver 2100 at the right side of the display area DA shown in FIG. 3.

In the middle area MA, grooves may be disposed between the region thatthe data lines DL detour and the opening area OA. The grooves mayprevent moisture from infiltrating through the opening area OA anddamaging the light-emitting device. In detail, the grooves maydisconnect (or isolate) a layer, through which the moisture may move,from among the layers on the substrate 100 (see FIG. 7), and thus, mayprevent the moisture from infiltrating into the display area DA. Forexample, the grooves may disconnect at least a part of the organicmaterial layer included in an intermediate layer 222 (see FIG. 7) thatwill be described later and/or an opposite electrode 223 (see FIG. 7).

Each of the first and second grooves G1 and G2 may have a closed loopshape surrounding the opening area OA in a plane view, and the first andsecond grooves G1 and G2 may be spaced apart from each other. In thisregard, FIG. 5 shows that one first groove G1 and one second groove G2surround the opening area OA, but one or more embodiments are notlimited thereto. For example, two or more first grooves G1 and/or secondgrooves G2 may be disposed in the middle area MA. In addition, in FIG.5, the second groove G2 is closer to the opening area OA than the firstgroove G1, and the first groove G1 surrounds the second groove G2, butarrangement order of the grooves is not restricted. For example, thefirst groove G1 may be closer to the opening area OA than the secondgroove G2, and the second groove G2 may surround the first groove G1.The first and second grooves G1 and G2 may have structures that are thesame as or different from each other, and detailed descriptions aboutthe structure of each of the first and second grooves G1 and G2 will bedescribed later with reference to FIG. 7.

FIG. 6 is a cross-sectional view showing a region of the display panel10 according to an embodiment. FIG. 6 is a cross-sectional view of thedisplay panel 10 taken along line VI-VI′ of FIG. 5.

The display panel 10 according to the embodiment includes the substrate100. The substrate 100 may include glass, metal, or a polymer resin.When the substrate 100 is flexible or bendable, the substrate 100 mayinclude a polymer resin such as a polyethersulfone, polyacrylate,polyetherimide, polyethylene naphthalate, polyethylene terephthalate,polyphynylene sulfide, polyarylate, polyimide, polycarbonate, orcellulose acetate propionate. The substrate 100 may be variouslymodified, for example, the substrate 100 may have a multi-layeredstructure including two layers each having a polymer resin and a barrierlayer including an inorganic material such as silicon oxide, siliconnitride, silicon oxynitride, etc. between the two layers.

In an embodiment, as shown in FIG. 6, the substrate 100 may include afirst base layer 101, a first barrier layer 102, a second base layer103, and a second barrier layer 104, which are sequentially stacked. Thefirst and second base layers 101 and 103 may each include a polymerresin. The first and second barrier layers 102 and 104 preventinfiltration of impurities from the outside, and may each include aninorganic material such as silicon oxide, silicon nitride, or siliconoxynitride in a single-layered or multi-layered structure.

A buffer layer 201 may be on the substrate 100. The buffer layer 201 mayimprove flatness of the upper surface of the substrate 100, or mayprevent or reduce infiltration of impurities or moisture into an activelayer from the outside of the substrate 100. The buffer layer 201 mayinclude an inorganic material such as silicon oxide, silicon nitride,and/or silicon oxynitride, and may have a single-layered ormulti-layered structure.

In the display area DA, the pixel circuit PC included in each of thepixels, and a light-emitting device electrically connected to the pixelcircuit PC, e.g., an organic light-emitting diode OLED may be on thesubstrate 100. As described above with reference to FIG. 4, the pixelcircuit PC may include a plurality of thin film transistors and astorage capacitor. In this regard, FIG. 6 shows a thin film transistorincluding a silicon-based semiconductor layer (hereinafter,silicon-based thin film transistor TFT), a thin film transistorincluding an oxide-based semiconductor layer (hereinafter, oxide-basedthin film transistor TFTo), and the storage capacitor Cst.

The silicon-based thin film transistor TFT may include a silicon-basedsemiconductor layer (hereinafter, first semiconductor layer Act), a gateelectrode (hereinafter, first gate electrode GE), a source electrode(hereinafter, first source electrode SE), and a drain electrode(hereinafter, first drain electrode DE) on the buffer layer 201.

The first semiconductor layer Act may include a channel region, and asource region and a drain region at opposite sides of the channelregion. The first semiconductor layer Act may include a silicon-basedsemiconductor material. For example, the first semiconductor layer Actmay include polysilicon (poly-Si) or amorphous silicon (amorphous-Si).

A first gate insulating layer 203 may be between the first semiconductorlayer Act and the first gate electrode GE. The first gate insulatinglayer 203 may include an inorganic insulating material such as siliconoxide, silicon nitride, and silicon oxynitride, and may have asingle-layered or multi-layered structure including above-statedinorganic insulating material.

The first gate electrode GE may overlap the channel region of the firstsemiconductor layer Act. The first gate electrode GE may include aconductive material including molybdenum (Mo), aluminum (Al), copper(Cu), titanium (Ti), etc., and may have a single-layered ormulti-layered structure including above-stated material. For example,the first gate electrode GE may include a Mo layer and an Al layer, or atriple-layered structure including Mo/Al/Mo.

The first source electrode SE and the first drain electrode DE are on aninorganic insulating layer covering the first gate electrode GE. Thefirst source electrode SE and the first drain electrode DE may beelectrically connected to a source region and a drain region of thefirst semiconductor layer Act via contact holes. The first sourceelectrode SE and the first drain electrode DE may include variousconductive materials including molybdenum (Mo), aluminum (Al), copper(Cu), titanium (Ti), etc., and may have various layered structures. Forexample, each of the first source electrode SE and the first drainelectrode DE may include a Ti layer and an Al layer, or a triple-layeredstructure including Ti/Al/Ti.

The storage capacitor Cst may include a lower electrode CE1 and an upperelectrode CE2 overlapping each other. In an embodiment, the lowerelectrode CE1 of the storage capacitor Cst may be integrally providedwith the first gate electrode GE. That is, the first gate electrode GEmay also function as the lower electrode CE1 of the storage capacitorCst, as well as the control electrode of the first thin film transistorTFT.

A first interlayer insulating layer 205 may be disposed between thelower electrode CE1 and the upper electrode CE2 of the storage capacitorCst. The first interlayer insulating layer 205 may include an inorganicinsulating material such as silicon oxide, silicon nitride, and siliconoxynitride, and may have a single-layered or multi-layered structureincluding above-stated inorganic insulating material.

The upper electrode CE2 of the storage capacitor Cst may have asingle-layered or multi-layered structure including a low-resistiveconductive material such as molybdenum (Mo), aluminum (Al), copper (Cu),and/or titanium (Ti).

A second interlayer insulating layer 207 may be on the storage capacitorCst. The second interlayer insulating layer 207 may include an inorganicinsulating material such as silicon oxide, silicon nitride, and siliconoxynitride, and may have a single-layered or multi-layered structureincluding above-stated inorganic insulating material.

The oxide-based thin film transistor TFTo may include an oxide-basedsemiconductor layer (hereinafter, second semiconductor layer Act′), agate electrode (hereinafter, second gate electrode GE′), a sourceelectrode (hereinafter, second source electrode SE′), and a drainelectrode (hereinafter, second drain electrode DE′).

The second semiconductor layer Act′ may be disposed on the secondinterlayer insulating layer 207. That is, the first semiconductor layerAct and the second semiconductor layer Act′ may be disposed at differentlayers from each other. The second semiconductor layer Act′ may includea channel region, and a source region and a drain region at oppositesides of the channel region. The second semiconductor layer Act′ mayinclude an oxide semiconductor material. For example, the secondsemiconductor layer Act′ may include Zn oxide-based material, e.g., Znoxide, In—Zn oxide, Ga—In—Zn oxide, etc. Alternatively, the secondsemiconductor layer Act′ may include In—Ga—Zn—O (IGZO), In—Sn—Zn—O(ITZO), or In—Ga—Sn—Zn—O (IGTZO) semiconductor including ZnO with metalsuch as indium (In), gallium (Ga), and tin (Zn).

The second gate insulating layer 209 may be disposed between the secondsemiconductor layer Act′ and the second gate electrode GE′. The secondgate insulating layer 209 may include an inorganic insulating materialsuch as silicon oxide, silicon nitride, and silicon oxynitride, and mayhave a single-layered or multi-layered structure including above-statedinorganic insulating material.

The second gate electrode GE′ may overlap the channel region of thesecond semiconductor layer Act′. The second gate electrode GE′ mayinclude a conductive material including molybdenum (Mo), aluminum (Al),copper (Cu), titanium (Ti), etc., and may have a single-layered ormulti-layered structure including above-stated material. For example,the second gate electrode GE′ may include a Mo layer and an Al layer, ora triple-layered structure including Mo/Al/Mo.

The second source electrode SE′ and the second drain electrode DE′ areon a third interlayer insulating layer 210 covering the second gateelectrode GE′. The second source electrode SE′ and the second drainelectrode DE′ may be electrically connected to a source region and adrain region of the second semiconductor layer Act′ via contact holes.The third interlayer insulating layer 210 may include an inorganicinsulating material such as silicon oxynitride, and may have asingle-layered or multi-layered structure including the inorganicinsulating material. Also, the second source electrode SE′ and thesecond drain electrode DE′ may include various conductive materialsincluding molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti),etc., and may have various layered structures. For example, the secondsource electrode SE′ and the second drain electrode DE′ may each includea Ti layer and an Al layer, or a triple-layered structure includingTi/Al/Ti.

Because the thin film transistor including the semiconductor layerincluding the silicon-based semiconductor material, like thesilicon-based thin film transistor TFT has high reliability, thesilicon-based thin film transistor TFT may be adopted as the drivingthin film transistor to implement a high-quality display panel.

Because the thin film transistor including the semiconductor layerhaving the oxide semiconductor material, like the oxide-based thin filmtransistor TFTo, has high carrier mobility and low leakage current,voltage drop does not increase even when the driving time increases.That is, because there is a small color change in the image due to thevoltage drop even in a low frequency driving, a low frequency driving ofthe oxide semiconductor is possible. As described above, because theoxide semiconductor has the low leakage current, the oxide semiconductormay be employed as at least one of the other thin film transistors thanthe driving thin film transistor so as to prevent the leakage currentand reduce power consumption.

A first organic insulating layer 211 may be disposed on the thirdinterlayer insulating layer 210. The first organic insulating layer 211may include an organic insulating material. The organic insulatingmaterial may include acryl, benzocyclobutene (BCB), hexamethyldisiloxane(HMDSO), or polyimide.

The data line DL, the driving voltage line PL, and the contact metallayer CM may be disposed on the first organic insulating layer 211, andmay be covered by a second organic insulating layer 213. The data lineDL, the driving voltage line PL, and the contact metal layer CM may eachinclude aluminum (Al), copper (Cu), and/or titanium (Ti), and may have asingle-layered or multi-layered structure including the above-statedmaterials. For example, each of the data line DL, the driving voltageline PL, and the contact metal layer CM may have a triple-layeredstructure including Ti/Al/Ti. In addition, the second organic insulatinglayer 213 may include an organic insulating material such as acryl, BCB,polyimide, and/or HMDSO.

The light-emitting device, e.g., the organic light-emitting diode OLED,may be disposed on the second organic insulating layer 213.

The pixel electrode 221 of the organic light-emitting diode OLED mayinclude a reflective layer including argentum (Ag), magnesium (Mg),aluminum (Al), platinum (Pt), palladium (Pd), aurum (Au), nickel (Ni),neodymium (Nd), iridium (Ir), chrome (Cr), or a compound thereof. Inanother embodiment, the pixel electrode 221 may further include aconductive oxide layer on and/or under the reflective layer. Theconductive oxide layer may include indium tin oxide (ITO), indium zincoxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium galliumoxide, and/or aluminum zinc oxide (AZO). In an embodiment, the pixelelectrode 221 may have a triple-layered structure including ITO layer/Aglayer/ITO layer.

A pixel defining layer 215 may be disposed on the pixel electrode 221.An opening overlapping the pixel electrode 221 is defined in the pixeldefining layer, but the opening covers edges of the pixel electrode 221.The pixel defining layer 215 may include an organic insulating material.

An intermediate layer 222 includes an emission layer 222 b. Theintermediate layer 222 may include a first functional layer 222 a underthe emission layer 222 b and/or a second functional layer 222 c on theemission layer 222 b. The emission layer 222 b may include a polymer orlow-molecular weight organic material emitting predetermined colorlight. The second functional layer 222 c may include an electrontransport layer (ETL) and/or an electron injection layer (EIL). Thefirst functional layer 222 a and the second functional layer 222 c mayeach include an organic material.

The opposite electrode 223 may include a conductive material having alow work function. For example, the opposite electrode 223 may include a(semi-)transparent layer including argentum (Ag), magnesium (Mg),aluminum (Al), platinum (Pt), palladium (Pd), aurum (Au), nickel (Ni),neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca),or an alloy thereof. Alternatively, the opposite electrode 223 mayfurther include a layer including ITO, IZO, ZnO, or In₂O₃ on the(semi-)transparent layer including the above material.

The emission layer 222 b may be disposed on the display area DA so as tooverlap the pixel electrode 221 via the opening in the pixel defininglayer 215. On the other hand, the first functional layer 222 a, thesecond functional layer 222 c, and the opposite electrode 223 may extendto the middle area MA, beyond the display area DA.

A spacer 217 may be disposed on the pixel defining layer 215. The spacer217 may be formed simultaneously with the pixel defining layer 215through the same process, or may be separately formed from the pixeldefining layer 215 through a separate process. In an embodiment, thespacer 217 may include an organic insulating material such as polyimide.

The organic light-emitting diode OLED may be covered by an encapsulationlayer 300. The encapsulation layer 300 may include at least one organicencapsulation layer and at least one inorganic encapsulation layer. Inan embodiment, FIG. 6 shows that the encapsulation layer 300 includesfirst and second inorganic encapsulation layers 310 and 330 and anorganic encapsulation layer 320 disposed between the first and secondinorganic encapsulation layers 310 and 330.

The first and second inorganic encapsulation layers 310 and 330 mayinclude one or more inorganic materials from aluminum oxide, titaniumoxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, siliconnitride, and silicon oxynitride. The first inorganic encapsulation layer310 and the second inorganic encapsulation layer 330 may each have asingle-layered structure or a multi-layered structure including theabove-mentioned materials. The organic encapsulation layer 320 mayinclude a polymer-based material. The polymer-based material may includean acryl-based resin, an epoxy-based resin, polyimide, polyethylene,etc. In an embodiment, the organic encapsulation layer 320 may includeacrylate.

The first inorganic encapsulation layer 310 and the second inorganicencapsulation layer 330 may have different thicknesses. The thickness ofthe first inorganic encapsulation layer 310 may be greater than that ofthe second inorganic encapsulation layer 330. Alternatively, thethickness of the second inorganic encapsulation layer 330 may be greaterthan that of the first inorganic encapsulation layer 310, or the firstinorganic encapsulation layer 310 and the second inorganic encapsulationlayer 330 may have the same thickness.

The display panel 10 may include the substrate 100, the display elementlayer 20 including a circuit-diode layer 200 disposed on the substrate100, the circuit-diode layer 200 including pixel circuits andlight-emitting devices, and the encapsulation layer 300, and an inputsensing layer 40 disposed on the display element layer 20.

The input sensing layer 40 may include a first touch insulating layer401 disposed on the second inorganic encapsulation layer 330, a firstconductive layer 402 disposed on the first touch insulating layer 401, asecond touch insulating layer 403 disposed on the first conductive layer402, a second conductive layer 404 disposed on the second touchinsulating layer 403, and a third touch insulating layer 405 disposed onthe second conductive layer 404.

Each of the first touch insulating layer 401, the second touchinsulating layer 403, and the third touch insulating layer 405 mayinclude an inorganic insulating material and/or an organic insulatingmaterial. In an embodiment, the first touch insulating layer 401 and thesecond touch insulating layer 403 may each include an inorganicinsulating material such as silicon oxide, silicon nitride, and/orsilicon oxynitride, and the third touch insulating layer 405 may includean organic insulating material.

A touch electrode TE of the input sensing layer 40 may have a structureto which the first conductive layer 402 and the second conductive layer404 are connected. Alternatively, the touch electrode TE may be at oneof the first conductive layer 402 and the second conductive layer 404,and may include a metal line included in the corresponding conductivelayer. The first conductive layer 402 and the second conductive layer404 may each include aluminum (Al), copper (Cu), and/or titanium (Ti),and may have a single-layered or multi-layered structure including theabove-stated materials. For example, the first conductive layer 402 andthe second conductive layer 404 may each have a triple-layered structureincluding Ti layer/Al layer/Ti layer.

Referring to the middle area MA of FIG. 6, the middle area MA mayinclude a first sub-middle area SMA1 through which the detour portionsDL-C1 and DL-C2 of the data lines DL described above with reference toFIG. 5 pass.

The detour portions DL-C1 and DL-C2 of the data lines DL may be atdifferent layers from each other. One of the detour portions DL-C1 andDL-C2 of the adjacent data lines DL may be on the third interlayerinsulating layer 210 and the other may be on the first organicinsulating layer 211.

When the detour portions DL-C1 and DL-C2 of the data lines DL arealternately arranged with the insulating layers (e.g. first planarizedinsulating layer 211) therebetween, a pitch (Δd) between the detourportions DL-C1 and DL-C2 of the data lines DL may be reduced, andaccordingly, an area of the middle area MA may be efficiently used.

FIG. 7 is a cross-sectional view showing a region of the display panel10 according to an embodiment. FIG. 7 is a cross-sectional view of thedisplay panel 10 taken along line VII-VII′ of FIG. 5.

Referring to FIGS. 6 and 7, the middle area MA may include the firstsub-middle area SMA1 adjacent to the display area DA (see FIG. 6) and asecond sub-middle area SMA2 adjacent to the opening area OA. The detourportions DL-C1 and DL-C2 of the data lines DL described above withreference to FIG. 6 are in the first sub-middle area SMA1, and the firstand second grooves G1 and G2 and a barrier wall PW may be in the secondsub-middle area SMA2. In addition, the encapsulation layer 300 extendsto the middle area MA to cover the first groove G1, the second grooveG2, and/or the barrier wall PW.

Referring to FIG. 7, the first groove G1 is in the second sub-middlearea SMA2 that is adjacent to the first sub-middle area SMA1, and thesecond groove G2 is in the second sub-middle area SMA2 that is adjacentto the opening area OA. As described above, the number and arrangingrelations of the first groove G1 and the second groove G2 may bevariously modified.

The first and second grooves G1 and G2 may be on a multi-layered filmincluding at least two layers having different materials. Themulti-layered film on which the first and second grooves G1 and G2 maycorrespond to some of the components included in the display panel 10.In an embodiment, the first groove G1 may be on the inorganic insulatinglayer that is on the substrate 100, and the second groove G2 may be onthe multi-layered film included in the substrate 100.

The first groove G1 may penetrate through at least one insulating layeron the substrate 100. The at least one insulating layer in which thefirst groove G1 is formed includes the first organic insulating layer211, and may further include insulating layer(s) under the first organicinsulating layer 211. Regarding this, FIG. 7 shows that the first grooveG1 is on the second interlayer insulating layer 207 and penetratesthrough the second gate insulating layer 209, the third interlayerinsulating layer 210, and the first organic insulating layer 211. Inthis case, the second gate insulating layer 209, the third interlayerinsulating layer 210, and the first organic insulating layer 211 mayrespectively include holes overlapping one another, and the holes arespatially connected to one another to form the first groove G1.

The first groove G1 may be obtained through an etching process, in whichthe second gate insulating layer 209, the third interlayer insulatinglayer 210, and the first organic insulating layer 211 are partiallyremoved.

In an embodiment, a lower layer 120 may be immediately under the firstgroove G1. The lower layer 120 may act as an etch stopper in the etchingprocess for forming the first groove G1. Therefore, a bottom surface ofthe first groove G1 may be an upper surface of the lower layer 120.Unlike in FIG. 7, when there are a plurality of first grooves G1, thelower layer 120 may be under each of the first grooves G1.

The lower layer 120 is on the second interlayer insulating layer 207,and may be formed simultaneously with the second semiconductor layerAct′ (see FIG. 6) described above with reference to FIG. 6 through thesame process. In an embodiment, the lower layer 120 may include the samematerial as that of the second semiconductor layer Act′, e.g., oxidesemiconductor material. In addition, the lower layer 120 may have aclosed loop shape surrounding the opening area OA in a plan view, likethe first groove G1.

In an embodiment, a metal dummy stack 110 may be adjacent to the firstgroove G1. For example, the metal dummy stacks 110 may be respectivelyat opposite sides of the first groove G1. The metal dummy stack 110 is akind of mound which may increase a depth of the first groove G1 and mayfunction as a crack detector. In an embodiment, FIG. 7 shows that themetal dummy stack 110 includes three metal layers overlapping withinsulating layers therebetween, e.g., first, second, and third metallayers 111, 112, and 113.

The first, second, and third metal layers 111, 112, and 113 may bedisposed at the same layers as those of the transistors and theelectrodes of the storage capacitor described above with reference toFIG. 6, and may include the same material. For example, the first metallayer 111 may be disposed at the same layer as the first sourceelectrode SE, the first drain electrode DE, the second source electrodeSE′, or the second drain electrode DE′, and may include the samematerial as that of the first source electrode SE, the first drainelectrode DE, the second source electrode SE′, or the second drainelectrode DE′. The second metal layer 112 may be at the same layer andmay include the same material as that of the second gate electrode GE′.The third metal layer 113 may be disposed at the same layer and mayinclude the same material as that of the upper electrode CE2 of thestorage capacitor Cst. FIG. 7 shows that the metal dummy stack 110includes three metal layers overlapping one another with insulatinglayers therebetween, but one or more embodiments are not limitedthereto. In another embodiment, the number of the metal layers in themetal dummy stack 100 may be less than or may exceed three.

The first groove G1 is not disposed on the substrate 100, but on theinorganic insulating layer that is disposed on the substrate 100. Thus,the moisture that may be flowed in through the substrate 100 may beblocked by at least one inorganic insulating layer. In this regard, FIG.7 shows the structure, in which the first groove G1 is disposed on thebuffer layer 201, the first gate insulating layer 203, and the firstinterlayer insulating layer 205, and the buffer layer 201, the firstgate insulating layer 203, and the first interlayer insulating layer 205may effectively block the moisture that may be flowed in through thesubstrate 100.

The first groove G1 may include at least one first tip PT1. In anembodiment, as shown in FIG. 7, the first groove G1 may have first tipsPT1 that are at opposite sides of a virtual vertical line VXL thatpasses through a center of the first groove G1. In another embodiment,the first groove G1 may include only one first tip PT1 located at aside.

The first tip PT1 may be provided in the metal pattern layer 212 that isimmediately on the first organic insulating layer 211. The metal patternlayer 212 may be disposed at the same layer and may include the samematerial as that of the data line DL (see FIG. 6), the driving voltageline PL (see FIG. 6), and/or the contact metal layer CM (see FIG. 6). Inan embodiment, the metal pattern layer 212 may have a triple-layeredstructure including Ti layer/Al layer/Ti layer.

The metal pattern layer 212 may be on at least one side of the firstgroove G1. For example, the metal pattern layers 212 may be disposed atopposite sides of the virtual vertical line VXL that passes through thecenter of the first groove G1, and an end of each of the metal patternlayer 212 protrudes toward the center of the first groove G1 to form thefirst tip PT1. The first tip PT1 is a kind of eaves portion which mayprotrude toward the center of the first groove G1 beyond the innersurface of the first organic insulating layer 211, which configures theinner surface of the first groove G1.When the first tips PT1 are atopposite sides of the first groove G1, the first groove G1 may includeholes respectively in the metal pattern layer 212, the second gateinsulating layer 209, the third interlayer insulating layer 210, and thefirst organic insulating layer 211. In addition, the holes may overlapone another and may be connected to one another.

The first groove G1 may be formed before the process of forming theintermediate layer 222, and the intermediate layer 222 and the oppositeelectrode 223 may be obtained by a thermal deposition method. At leastone organic material layer included in the intermediate layer and/or theopposite electrode 223 are disconnected by the first tips PT1 of thefirst groove G1, and thus, the proceeding of the moisture toward thedisplay area DA (see FIG. 5) may be prevented. In this regard, FIG. 7shows that the first functional layer 222 a, the second functional layer222 c, and the opposite electrode 223 are disconnected by the first tipPT1 of the first groove G1, but one or more embodiments are not limitedthereto. For example, one of the first functional layer 222 a and thesecond functional layer 222 c may be omitted.

The inorganic encapsulation layer included in the encapsulation layer300 may have a relatively superior step coverage to those of the firstfunctional layer 222 a, the second functional layer 222 c, and/or theopposite electrode 223, and may not be disconnected by the first grooveG1. In an embodiment, as shown in FIG. 7, the first inorganicencapsulation layer 310 may not be disconnected by the first groove G1,but may be continuously provided. In detail, the first inorganicencapsulation layer 310 may continuously cover inner and lower surfacesof the metal pattern layer 212, the inner surface of the first organicinsulating layer 211, the inner surface of the third interlayerinsulating layer 210, and the inner surface of the second gateinsulating layer 209, along with the shape of the first groove G1.

The second groove G1 may be disposed on a multi-layered film included inthe substrate 100. In this regard, FIG. 7 shows that the second grooveG2 is in the multi-layered film including the second base layer 103 andthe second barrier layer 104, but one or more embodiments are notlimited thereto.

In an embodiment, as shown in FIG. 7, the second groove G2 may have arecess that is concave in a thickness direction of the second base layer103 and a hole penetrating through the second barrier layer 104. Here,‘recess’ denotes a groove partially formed in the second base layer 103in the thickness direction. That is, in a portion where the recess isformed, a remaining part of the second base layer 103 in the thicknessdirection may cover a layer under the second base layer 103 (e.g., firstbarrier layer 102). The recess that is concave in the thicknessdirection of the second base layer 103 may be obtained by forming a holepenetrating through the second barrier layer 104 by etching the secondbarrier layer 104 and then partially etching the second base layer 103.The recess in the second base layer 103 and the hole in the secondbarrier layer 104 may be spatially connected to each other to form thesecond groove G2. The etching may be performed by an isotropic etchingmethod and/or an anisotropic etching method.

In another embodiment, unlike the example shown in FIG. 7, the secondgroove G2 may include a hole penetrating through the second base layer103 and a hole penetrating through the second barrier layer 104. Thehole penetrating through the second barrier layer 104 may be obtained byetching the second barrier layer, and the hole penetrating through thesecond base layer 103 may be obtained by etching the second base layer103. The hole in the second base layer 103 and the hole in the secondbarrier layer 104 may be spatially connected to each other to form thesecond groove G2.

A cross-section of the second groove G2 may have an undercut shape thatis concave in the thickness direction of the multi-layered film. Aninner surface of the hole penetrating through the second barrier layer104 may protrude more than the inner surface of the recess concave inthe thickness direction of the second base layer 103 or the innersurface of the hole penetrating through the second base layer 103, inthe direction (e.g., x-direction) parallel to the upper surface (orlower surface) of the substrate 100. The protruding portions of thesecond barrier layer 104 toward the center of the second groove G2 mayform second tips PT2.

The second groove G2 may be formed before the process of forming theintermediate layer 222, and the intermediate layer 222 and the oppositeelectrode 223 may be obtained by a thermal deposition method. At leastone organic material layer included in the intermediate layer and/or theopposite electrode 223 are disconnected by the second tips PT2 of thesecond groove G2, and thus, the proceeding of the moisture toward thedisplay area DA (see FIG. 5) may be prevented. In this regard, FIG. 7shows that the first functional layer 222 a, the second functional layer222 c, and the opposite electrode 223 are disconnected by the second tipPT2 of the second groove G2, but one or more embodiments are not limitedthereto. For example, one of the first functional layer 222 a and thesecond functional layer 222 c may be omitted.

The inorganic encapsulation layer included in the encapsulation layer300 may have a relatively superior step coverage to those of the firstfunctional layer 222 a, the second functional layer 222 c, and/or theopposite electrode 223, and may not be disconnected by the second grooveG2. In an embodiment, as shown in FIG. 7, the first inorganicencapsulation layer 310 may not be disconnected by the second groove G2,but may be continuously provided. In detail, the first inorganicencapsulation layer 310 may continuously cover inner and lower surfacesof the metal pattern layer 212, the inner surface of the first organicinsulating layer 211, the inner surface of the third interlayerinsulating layer 210, and the inner surface of the second gateinsulating layer 209, along with the shape of the first groove G1.

FIGS. 8, 9, and 10 are cross-sectional views sequentially showing someof processes of manufacturing the display panel 10 of FIG. 7. FIGS. 8,9, and 10 only illustrate a part of the middle area MA, and in thedisplay area DA (see FIG. 6), the components at the same layer may beformed together.

As shown in FIG. 8, a plurality of insulating layers and the metal dummystack 110, the lower layer 120, and the metal pattern layer 212 areformed on the substrate 100, and the second organic insulating layer 213covering the metal pattern layer 212 is formed. The second organicinsulating layer 213 has an opening that overlaps a portion where thefirst groove G1 is to be formed, and each of the second barrier layer104, the buffer layer 201, the inorganic insulating layers 203, 205, and207 on the buffer layer 201 has an opening overlapping a portion wherethe second groove G2 is to be formed.

In addition, the second organic insulating layer 213 covers edges of themetal pattern layer 212. Accordingly, the first tip PT1 of the metalpattern layer 212 is not exposed in post-processes and may be protectedby the second organic insulating layer 213.

Next, as shown in FIG. 9, a mask layer 250 is formed on the secondorganic insulating layer 213. The mask layer 250 is a layer arrangedduring manufacturing processes to perform as a mask and then is removed.The mask layer 250 may have a pattern corresponding to portions wherethe first tip PT1 of the first groove G1 and the second tip PT2 of thesecond groove G2 are to be formed. In an embodiment, the mask layer 250may include indium zinc oxide (IZO).

In addition, as shown in FIG. 10, an etching process is performed in astate in which the mask layer 250 is arranged, to form the first grooveG1 and the second groove G2. That is, the first groove G1 and the secondgroove G2 may be simultaneously formed through the same process. In anembodiment, the etching may be performed by a wet etching method and/oran isotropic etching method, but is not limited thereto. In anotherembodiment, the etching may be performed by a dry etching method and/oran anisotropic etching method.

During the etching process, the insulating layers under the mask layer250 are at least partially etched to form the grooves. In detail, aportion overlapping the mask layer 250 is not etched, and a portion notoverlapping the mask layer 250 may be etched to form the groove. In thisregard, FIG. 10 shows that each of the second gate insulating layer 209,the third interlayer insulating layer 210, and the first organicinsulating layer 211 is partially etched to form the first groove G1 andeach of the buffer layer 201, the first gate insulating layer 203, thefirst interlayer insulating layer 205, and the second interlayerinsulating layer 207 is partially etched to form the second groove G2.

Through the above etching process, the first groove G1 and the secondgroove G2 may each have an undercut shape that is concave in thethickness direction. Also, the first groove G1 includes the first tipPT1 that is a protrusion from the metal pattern layer 212 toward thecenter of the first groove G1, and the second groove G2 includes thesecond tip PT2 that is a protrusion from the first gate insulating layer203 toward the center of the second groove G2.

FIG. 11 is a cross-sectional view showing a region of the display panel10 according to an embodiment. FIG. 11 is a cross-sectional view of thedisplay panel 10 taken along line VII-VII′ of FIG. 5. In addition, FIG.11 is different from the example of FIG. 7 only in view of a tipstructure in the first groove G1, and the difference will be describedbelow in detail.

Referring to FIG. 11, the first groove G1 may have a first tip PT1′having a multi-layered structure 510 including a concave portion. Thefirst tip PT1′ of the first groove G1 may be in the metal pattern layer212. The metal pattern layer 212 may include the same material as thatof the data line DL, the driving voltage line PL, and/or the contactmetal layer CM described above with reference to FIG. 6. In anembodiment, the metal pattern layer 212 may have the multi-layeredstructure 510 including a first layer 511 including titanium (Ti), asecond layer 512 including aluminum (Al), and a third layer 513including titanium (Ti) that are sequentially stacked.

The multi-layered structure 510 may have a concave portion that isobtained when the second layer 512 is depressed toward the center of thesecond layer 512. The first layer 511 and the third layer 513 mayfurther protrude than the second layer 512 in the direction toward thecenter of the first groove G1, and then, the tip may be obtained. Inthis case, a width of the second layer 512 may be smaller than those ofthe first layer 511 and the third layer 513.

The concave portion of the multi-layered structure 510 may be obtainedby an etching, e.g., an isotropic etching process, and the concaveportion may be formed according to an etch ratio between the layersincluded in the multi-layered structure 510. For example, the secondlayer 512 of the multi-layered structure 510 may include a materialhaving an etch rate greater than those of the first layer 511 and thethird layer 513, and thus, the second layer 512 may be further etchedrelatively and depressed in a direction away from the center of thefirst groove G1.

From among the layers in the multi-layered structure 510, a layerincluding a material having relatively large etch rate may be exposedand further etched in post-processes. For example, the second layer 512of the multi-layered structure 510 includes aluminum (Al) as a materialhaving relatively fast etch rate, and the first layer 511 and the thirdlayer 513 in the multi-layered structure 510 may include titanium (Ti)as a material having relatively slow etch rate. In an embodiment, in anetching process (e.g., wet-etching process) for patterning the pixelelectrode 221 in post-processes, the second layer 512 including aluminum(Al) is additionally etched, but the first layer 511 and the third layer513 including titanium (Ti) may not be additionally etched. Accordingly,the second layer 512 may have a shape that is further depressed in adirection away from the center of the first groove G1. The effect thatthe layers exposed in the post-processes are differentially furtheretched due to the difference between the etch rates of the layers may bealso applied to a first stack structure 610 (see FIG. 20), a secondstack structure 620 (see FIG. 20), and a third stack structure 630 (seeFIG. 20).

The concave portion of the multi-layered structure 510 may be formedbefore the process of forming the intermediate layer 222, and theintermediate layer 222 and the opposite electrode 223 may be obtained bya thermal deposition method. The at least one organic material layerincluded in the intermediate layer and/or the opposite electrode 223 maybe disconnected at one point of the concave portion in the multi-layeredstructure 510 and discontinuously formed.

In an embodiment, the multi-layered structure 510 may be at the samelayer, may have the same multi-layered structure, and may include thesame material as those of the data line DL, the driving voltage line PL,and/or the contact metal layer CM. For example, the data line DL, thedriving voltage line PL, and/or the contact metal layer CM may eachinclude a Ti layer, an Al layer, and a Ti layer that are sequentiallystacked.

FIGS. 12, 13, and 14 are cross-sectional views sequentially showing someof processes of manufacturing the display panel of FIG. 11.

As shown in FIG. 12, a plurality of insulating layers and the metaldummy stack 110, the lower layer 120, and the metal pattern layer 212are formed on the substrate 100, and the second organic insulating layer213 covering the metal pattern layer 212 is formed. An opening thatoverlaps a portion where the first groove G1 is to be formed is definedin the second organic insulating layer 213, and an opening overlapping aportion where the second groove G2 is to be formed is defined in each ofthe second barrier layer 104, the buffer layer 201, the inorganicinsulating layers 203, 205, and 207 disposed on the buffer layer 201. Inaddition, the metal pattern layer 212 has a triple-layered structureincluding Ti layer/Al layer/Ti layer.

In addition, the second organic insulating layer 213 does not coveredges of the metal pattern layer 212. That is, the opening of the secondorganic insulating layer 212 is wider than the opening in the metalpattern layer 212, and exposes the first tip PT1′ of the metal patternlayer 212. Accordingly, the first tip PT1′ of the metal pattern layer212 may be exposed during post-processes.

In addition, as shown in FIG. 13, the multi-layered structure 510 havinga concave portion at the end of the first tip PT1′ may be formed duringperforming the post-processes.

As described above, from among the layers in the multi-layered structure510, a layer including a material having relatively large etch rate maybe exposed and further etched in post-processes. In this regard, in FIG.13, the first tip PT1′ of the metal pattern layer 212 is exposed in thepost-processes, and thus, the second layer 512 is additionally etchedand the concave portion is formed. The second layer 512 of themulti-layered structure 510 includes aluminum (Al) as a material havingrelatively fast etch rate, and the first layer 511 and the third layer513 in the multi-layered structure 510 may include titanium (Ti) as amaterial having relatively slow etch rate. In an embodiment, in anetching process (e.g., wet-etching process) for patterning the pixelelectrode 221 in post-processes, the second layer 512 including aluminum(Al) is additionally etched, but the first layer 511 and the third layer513 including titanium (Ti) may not be additionally etched. Accordingly,the second layer 512 may have a shape that is further depressed in adirection away from the center of the first groove G1.

Next, the mask layer 250 is formed on the second organic insulatinglayer 213. The mask layer 250 is a layer arranged during manufacturingprocesses to perform as a mask and then is removed. The mask layer 250may have a pattern corresponding to portions where the first tip PT1′ ofthe first groove G1 and the second tip PT2 of the second groove G2 areto be formed. In an embodiment, the mask layer 250 may include indiumzinc oxide (IZO).

In addition, as shown in FIG. 14, an etching process is performed in astate in which the mask layer 250 is arranged, to form the first grooveG1 and the second groove G2. That is, the first groove G1 and the secondgroove G2 may be simultaneously formed through the same process. Duringthe etching process, the insulating layers under the mask layer 250 areat least partially etched to form the grooves. In detail, a portionoverlapping the mask layer 250 is not etched, and a portion notoverlapping the mask layer 250 may be etched to form the groove. In thisregard, FIG. 14 shows that each of the second gate insulating layer 209,the third interlayer insulating layer 210, and the first organicinsulating layer 211 is partially etched to form the first groove G1 andeach of the buffer layer 201, the first gate insulating layer 203, thefirst interlayer insulating layer 205, and the second interlayerinsulating layer 207 is partially etched to form the second groove G2.

In an embodiment, the etching may be performed by the wet etching methodand/or the isotropic etching method. Accordingly, an undercut shape thatis concave in the thickness direction may be obtained. In addition, thefirst groove G1 includes the first tip PT1′ that is a protrusion fromthe metal pattern layer 212 toward the center of the first groove G1,and the second groove G2 includes the second tip PT2 that is aprotrusion from the first gate insulating layer 203 toward the center ofthe second groove G2.

FIG. 15 is a plan view showing a region of the display panel 10according to an embodiment, and FIG. 16 is a cross-sectional viewshowing a region of the display panel 10 according to the embodiment.FIG. 16 is a cross-sectional view of the display panel 10 taken alongline VIII-VIII′ of FIG. 15. Also, the embodiment as shown in FIGS. 15and 16 is only different in view of further including a disconnectionportion 600 as compared with the embodiment of FIG. 7, and thus,difference will be described below.

Referring to FIGS. 15 and 16, the display panel 10 according to theembodiment may further include the disconnection portion 600.

The disconnection portion 600 may be in the middle area MA. Thedisconnection portion 600 has a closed loop shape surrounding theopening area OA in a plan view, and may be spaced apart from the firstand second grooves G1 and G2 described above. The number and arrangementorder of the disconnection portion 600 are not restricted. In anembodiment, as shown in FIG. 15, one disconnection portion 600 surroundsthe opening area OA, and the first and second grooves G1 and G2 maysurround the disconnection portion 600. In another embodiment, aplurality of disconnection portions 600 may be provided. In addition,the disconnection portion 600 may be between the first groove G1 and thesecond groove G2, or may surround the first groove G1 and the secondgroove G2. In another embodiment, one of the first groove G1 and thesecond groove G2 may be omitted. For example, the display panel 10 mayonly include the first groove G1 and the disconnection portion 600, orthe second groove G2 and the disconnection portion 600.

The disconnection portion 600 may be on the inorganic insulating layerthat is on the substrate 100. In this regard, FIG. 16 shows that thedisconnection portion 600 is on the second interlayer insulating layer207, but one or more embodiments are not limited thereto. In anotherembodiment, the disconnection portion 600 may be on the substrate 100,the buffer layer 201, the first gate insulating layer 203, the firstinterlayer insulating layer 205, the second gate insulating layer 209,or the third interlayer insulating layer 210.

The disconnection portion 600 may include at least one stack structurein which a plurality of sub-layers are stacked. In this regard, FIG. 16shows an example in which the disconnection portion 600 only includesthe second stack structure 620. Referring to FIG. 16, an electrodepattern layer 111 a may be on the second interlayer insulating layer207. In an embodiment, the electrode pattern layer 111 a may have thesame layered structure and include the same material as those of thefirst source electrode SE (see FIG. 6), the first drain electrode DE(see FIG. 6), the second source electrode SE′ (see FIG. 6), or thesecond drain electrode DE′ (see FIG. 6). For example, the electrodepattern layer 111 a may have a triple-layered structure including Tilayer/AI layer/Ti layer.

The organic pattern layer 211 a is on the second interlayer insulatinglayer 207 and may cover an edge of the electrode pattern layer 111 a.The organic pattern layer 211 a may have an opening that exposed acenter portion of the electrode pattern layer 111 a. In an embodiment,the organic pattern layer 211 a may have the same layered structure andinclude the same material as those of the first organic insulating layer211. Such above organic pattern layer 211 a may generate a step betweenan upper surface and a bottom surface of the second stack structure 620(see FIG. 17).

The second stack structure 620 may cover an upper surface of the organicpattern layer 211 a, an internal surface of the organic pattern layer211 a in the direction to the opening, and an upper surface of theelectrode pattern layer 111 a, which is exposed by the opening of theorganic pattern layer 211 a.

FIG. 17 is a cross-sectional view showing a region of the disconnectionportion 600 according to an embodiment, FIG. 18A is a cross-sectionalview showing a region of the disconnection portion 600 according toanother embodiment, and FIG. 18B is a cross-sectional view showing aregion of the disconnection portion 600 according to another embodiment.FIGS. 17, 18A, 18B, 19, 20, 21, and 22 are enlarged views of region A inFIG. 16.

Each of the stack structures may have a shape that may disconnect a partof the intermediate layer 222 and/or the opposite electrode 223 coveringthe disconnection portion 600. In detail, each of the stack structuresmay have concave portions in a side surface in the direction toward theopening area OA and a side surface opposite to the opening area OA.

In an embodiment, the disconnection portion 600 may have at least one ofthe first stack structure 610, in which a 1-1st sub-layer 611, a 1-2ndsub-layer 612, and a 1-3rd sub-layer 613 are sequentially stacked, and asecond stack structure 620, in which a 2-1st sub-layer 621, a 2-2ndsub-layer 622, and a 2-3rd sub-layer 623 are sequentially stacked. Thesecond stack structure 620 may be on the first stack structure 610.

Referring to FIGS. 17, 18A, and 18B, the first stack structure 610 mayhave a first concave portion that is formed by denting the 1-2ndsub-layer 612 toward the center of the 1-2nd sub-layer 612. The 1-1stsub-layer 611 and the 1-3rd sub-layer 613 may further protrude than the1-2nd sub-layer 612 in the direction toward the opening area OA and thedirection opposite to the opening area OA to form the tip. In this case,a width of the 1-2nd sub-layer 612 may be less than that of the 1-1stsub-layer 611 and that of the 1-3rd sub-layer 613. Likewise, the secondstack structure 620 may have a second concave portion that is formed bydenting the 2-2nd sub-layer 622 toward the center of the 2-2nd sub-layer622. The 2-1st sub-layer 621 and the 2-3rd sub-layer 623 may furtherprotrude than the 2-2nd sub-layer 622 in the direction toward theopening area OA and the direction opposite to the opening area OA toform the tip. In this case, a width of the 2-2nd sub-layer 622 may beless than that of the 2-1st sub-layer 621 and the 2-3rd sub-layer 623.

The disconnection portion 600 may be formed by etching, e.g., theisotropic etching process, and the concave portions may be formedaccording to an etch ratio between the sub-layers. For example, the1-2nd sub-layer 612 of the first stack structure 610 may include amaterial having faster etch rate than that of the 1-1st sub-layer 611and the 1-3rd sub-layer 613, and thus, may be relatively more etched anddepressed toward the center of the 1-2nd sub-layer 612. Likewise, the2-2nd sub-layer 622 of the second stack structure 620 may include amaterial having faster etch rate than that of the 2-1st sub-layer 621and the 2-3rd sub-layer 623, and thus, may be relatively more etched anddepressed toward the center of the 2-2nd sub-layer 622. As describedabove, the sub-layers including the material having relative fast etchrate may be exposed during the post-process (e.g., an etching processfor patterning the pixel electrode) and may be additionally etched.

In an embodiment, the first stack structure 610 may have the same stackstructure and include the same material as those of the first sourceelectrode SE (see FIG. 6), the first drain electrode DE (see FIG. 6),the second source electrode SE′ (see FIG. 6), and/or the second drainelectrode DE′ (see FIG. 6). In detail, the first stack structure 610 mayhave a structure, in which the 1-1st sub-layer 611 including titanium(Ti), the 1-2nd sub-layer 612 including aluminum (Al), and the 1-3rdsub-layer 613 including titanium (Ti) are sequentially stacked. Inaddition, each of the first source electrode SE, the first drainelectrode DE, the second source electrode SE′, and/or the second drainelectrode DE′ may have a structure, in which a layer including the samematerial as that of the 1-1st sub-layer 611, a layer including the samematerial as that of the 1-2nd sub-layer 612, and a layer including thesame material as that of the 1-3rd sub-layer 613 are sequentiallystacked.

Also, the second stack structure 620 may have the same stack structureand the same material as those of the data line DL (see FIG. 6), thedriving voltage line PL (see FIG. 6), and/or the contact metal layer CM(see FIG. 6). In detail, the second stack structure 620 may have astructure, in which the 2-1st sub-layer 621 including titanium (Ti), the2-2nd sub-layer 622 including aluminum (Al), and the 2-3rd sub-layer 623including titanium (Ti) are sequentially stacked. In addition, thecontact metal layer CM may have a structure, in which a layer includingthe same material as that of the 2-1st sub-layer 621, a layer includingthe same material as that of the 2-2nd sub-layer 622, and a layerincluding the same material as that of the 2-3rd sub-layer 623 aresequentially stacked.

The disconnection portion 600 having the above structure may be formedbefore the process of forming the intermediate layer 222, and theintermediate layer 222 and the opposite electrode 223 may be obtained bya thermal deposition method. The at least one organic material layerincluded in the intermediate layer and/or the opposite electrode 223 maybe disconnected by the disconnection portion 600 and discontinuouslyformed.

In an embodiment, as shown in FIG. 18A, layers having bad step coveragesmay have decreased thickness toward the inside of the concave portions,and may be disconnected in at least one of the concave portions. Forexample, because the intermediate layer 222 and/or the oppositeelectrode 223 extending while covering the stack structure may haveinferior step coverage as compared with the first inorganicencapsulation layer 310 and the second inorganic encapsulation layer330, thickness is reduced toward the inside of the concave portions andmay be disconnected and discontinuously formed in at least one of theconcave portions. For example, each of the intermediate layer 222 and/orthe opposite electrode 223 may have a thickness that is graduallyreduced and then disconnected toward the inside of the first concaveportion of the first stack structure 610 or the inside of the secondconcave portion of the second stack structure 620. In addition, thefirst inorganic encapsulation layer 310, the second inorganicencapsulation layer 330, and the first touch insulating layer 401 havingrelatively excellent step coverage may be continuously formed along theshape of the disconnection portion 600.

In another embodiment, as shown in FIG. 18B, the intermediate layer 222and/or the opposite electrode 223 may be disconnected by the tips atupper and lower portions of the concave portion. For example, referringto FIG. 18B, the intermediate layer 222 and the opposite electrode 223cover the upper surface of the disconnection portion 600 and may bedisconnected and discontinuously formed due to the tips at opposite endsof the upper surface of the disconnection portion 600. In addition, thefirst inorganic encapsulation layer 310, the second inorganicencapsulation layer 330, and the first touch insulating layer 401 havingrelatively excellent step coverage may be continuously formed along theshape of the disconnection portion 600.

Hereinafter, FIGS. 19, 20, 21, and 22 show a case in which the layershaving bad step coverage have a thickness that is reduced toward theinside of the concave portions and are disconnected inside at least oneof the concave portions as shown in FIG. 18A, but the layers coveringthe disconnection portion 600 may be formed as shown in FIG. 18B instructures that will be described later.

FIG. 19 is a cross-sectional view partially showing the disconnectionportion 600 according to another embodiment. The embodiment as shown inFIG. 19 is only different from that of FIG. 18A in view of widths of thestack structures.

In the embodiment illustrated in FIG. 18A, a width w1 of the first stackstructure 610 is equal to a width w2 of the second stack structure 620,but one or more embodiments are not limited thereto. Here, the width w1of the first stack structure 610 denotes a width of the upper surface ofthe 1-1st sub-layer 611 and a width of the upper surface of the 1-3rdsub-layer 613, and the width w2 of the second stack structure 620 maydenote a width of the upper surface of the 2-1st sub-layer 621 and awidth of the upper surface of the 2-3rd sub-layer 623. For example, asshown in FIG. 19, the width w2 of the second stack structure 620 may beless than the width w1 of the first stack structure 610. In addition,unlike the example shown in FIG. 9, the width w2 of the second stackstructure 620 may be greater than the width w1 of the first stackstructure 610.

FIGS. 20, 21, and 22 are cross-sectional views a region of thedisconnection portion 600 according to one or more embodiments. Indetail, FIGS. 20, 21, and 22 are cross-sectional views showing a regionof the disconnection portion 600 further including a third stackstructure 630.

As shown in FIGS. 20, 21, and 22, the disconnection portion 600 mayinclude the first stack structure 610 on the substrate 100 (see FIG. 6),the second stack structure 620 on the first stack structure 610, and thethird stack structure 630 on the second stack structure 620. The thirdstack structure 630 may include a 3-1st sub-layer 631, a 3-2nd sub-layer632, and a 3-3rd sub-layer 633 that are sequentially stacked.

The third stack structure 630 may have a third concave portion that isobtained by denting the 3-2nd sub-layer 632 toward the center thereof,similarly to the first stack structure 610 and the second stackstructure 620. Descriptions about structural characteristics and effectsof the first concave portion in the first stack structure 610 and thesecond concave portion in the second stack structure 620 are applied tothe third concave portion.

According to the embodiment, the intermediate layer 222 and/or theopposite electrode 223 may each have a thickness that is graduallyreduced and then disconnected toward the inside of the first concaveportion of the first stack structure 610, the inside of the secondconcave portion of the second stack structure 620, or the inside of thethird concave portion of the third stack structure 630. As describedabove, when the disconnection portion 600 further includes the thirdstack structure 630, the number of concave portions increases, and thus,the intermediate layer 222 and/or the opposite electrode 223 may beeffectively disconnected.

In an embodiment, the third stack structure 630 may have the same stackstructure and the same material as those of the pixel electrode 221 (seeFIG. 6). In detail, the third stack structure 630 may have a structure,in which the 3-1st sub-layer 631 including ITO, the 3-2nd sub-layer 632including argentum (Ag), and the 3-3rd sub-layer 633 including ITO aresequentially stacked. In addition, the contact metal layer CM may have astructure, in which a layer including the same material as that of the3-1st sub-layer 631, a layer including the same material as that of the3-2nd sub-layer 632, and a layer including the same material as that ofthe 3-3rd sub-layer 633 are sequentially stacked.

In addition, as shown in FIG. 20, the width w1 of the first stackstructure 610, the width w2 of the second stack structure 620, and awidth w3 of the third stack structure 630 may be equal to one another,but are not limited thereto. For example, as shown in FIG. 21, the widthw2 of the second stack structure 620 and the width w3 of the third stackstructure 630 may be less than the width w1 of the first stack structure610. In addition, as shown in FIG. 22, the width w3 of the third stackstructure 630 may be less than the width w2 of the second stackstructure 620, and the width w2 of the second stack structure 620 may beless than the width w1 of the first stack structure 610.

The display apparatus has been described, but one or more embodiments ofthe disclosure are not limited thereto. For example, a method ofmanufacturing the display apparatus may be also included in the scope ofthe disclosure.

According to one or more embodiments of the disclosure, the displayapparatus having an improved performance of preventing moistureinfiltration may be implemented. However, the scope of one or moreembodiments is not limited to the above effects.

It should be understood that embodiments described herein should beconsidered in a descriptive sense only and not for purposes oflimitation. Descriptions of features or aspects within each embodimentshould typically be considered as available for other similar featuresor aspects in other embodiments. While one or more embodiments have beendescribed with reference to the figures, it will be understood by thoseof ordinary skill in the art that various changes in form and detailsmay be made therein without departing from the spirit and scope asdefined by the following claims.

What is claimed is:
 1. A display panel comprising: a substrate includinga display area and a middle area, wherein an opening is defined in thesubstrate, the display area surrounds the opening, and the middle areais disposed between the opening and the display area; a light-emittingdevice disposed in the display area, the light-emitting device includinga pixel electrode, an opposite electrode, and an intermediate layerdisposed between the pixel electrode and the opposite electrode; anencapsulation layer covering the light-emitting device, theencapsulation layer including at least one inorganic encapsulationlayer; a first groove disposed in the middle area, the first groovedisposed on the substrate; and a second groove disposed in the middlearea, the second groove having an undercut shape that is concave in athickness direction of a multi-layered film in the substrate.
 2. Thedisplay panel of claim 1, wherein the first groove includes: a 1-1sthole in an inorganic insulating layer on the substrate; and a 1-2nd holein an organic insulating layer on the inorganic insulating layer,wherein the 1-2nd hole is connected to the 1-1st hole.
 3. The displaypanel of claim 2, wherein the first groove includes a first tip thatprotrudes from a metal pattern layer disposed on the organic insulatinglayer toward a center of the first groove.
 4. The display panel of claim3, wherein an organic material layer included in the intermediate layeror the opposite electrode is disconnected by the first tip.
 5. Thedisplay panel of claim 3, wherein the at least one inorganicencapsulation layer continuously covers an inner surface and a lowersurface of the metal pattern layer and an inner surface of the organicinsulating layer.
 6. The display panel of claim 3, wherein the first tiphas a multi-layered structure, in which a first layer, a second layer,and a third layer are sequentially stacked, and a concave portion thatis obtained by denting the second layer in a direction away from thecenter of the first groove, and the organic material layer included inthe intermediate layer or the opposite electrode is disconnected by themulti-layered structure.
 7. The display panel of claim 1, furthercomprising a lower layer disposed under the first groove, the lowerlayer having an upper surface corresponding to a bottom surface of thefirst groove.
 8. The display panel of claim 1, further comprising metaldummy stacks at opposite sides of the first groove based on a line thatpasses through the center of the first groove and is perpendicular to anupper surface of the substrate, the metal dummy stacks each includingone or more metal layers stacked with an insulating layer therebetween.9. The display panel of claim 1, wherein the multi-layered film includedin the substrate includes a base layer and a barrier layer disposed onthe base layer.
 10. The display panel of claim 9, wherein the secondgroove includes: a 2-1st hole or a 2-1st recess in the base layer; and a2-2nd hole in the barrier layer, wherein the 2-2nd hole is connected tothe 2-1st hole or the 2-1st recess.
 11. The display panel of claim 10,wherein the second groove includes a second tip that is a protrusionfrom the barrier layer toward a center of the second groove.
 12. Thedisplay panel of claim 11, wherein an organic material layer included inthe intermediate layer or the opposite electrode is disconnected by thesecond tip.
 13. The display panel of claim 11, wherein the at least oneinorganic encapsulation layer continuously covers an inner surface and alower surface of the barrier layer and an inner surface of the baselayer.
 14. The display panel of claim 1, further comprising adisconnection portion in the middle area, and having at least one of afirst stack structure, in which a 1-1st sub-layer, a 1-2nd sub-layer,and a 1-3rd sub-layer are sequentially stacked, and a second stackstructure on the first stack structure, the second stack structureincluding a 2-1st sub-layer, a 2-2nd sub-layer, and a 2-3rd sub-layersequentially stacked, wherein an organic material layer included in theintermediate layer or the opposite electrode is disconnected by thedisconnection portion.
 15. The display panel of claim 14, wherein thefirst stack structure has a first concave portion formed by denting the1-2nd sub-layer toward a center thereof, and the second stack structurehas a second concave portion formed by denting the 2-2nd sub-layertoward a center thereof.
 16. The display panel of claim 14, furthercomprising a thin film transistor disposed on the substrate, the thinfilm transistor including a semiconductor layer, a gate electrodeoverlapping the semiconductor layer, and a source electrode and a drainelectrode electrically connected to the semiconductor layer, Whereineach of the source electrode and the drain electrode has a structure, inwhich a layer having a material same as a material in the 1-1stsub-layer, a layer having a material same as a material in the 1-2ndsub-layer, and a layer having a material same as a material in the 1-3rdsub-layer are sequentially stacked.
 17. The display panel of claim 16,further comprising a contact metal layer on the thin film transistor,the contact metal layer being electrically connected to the sourceelectrode or the drain electrode, wherein the contact metal layer has astructure, in which a layer having a material same as a material in the2-1st sub-layer, a layer having a material same as a material in the2-2nd sub-layer, and a layer having a material same as a material in the2-3rd sub-layer are sequentially stacked.
 18. The display panel of claim14, wherein the disconnection portion further includes a third stackstructure disposed on the second stack structure, the third stackstructure including a 3-1st sub-layer, a 3-2nd sub-layer, and 3-3rdsub-layer sequentially stacked.
 19. The display panel of claim 18,wherein the first stack structure has a first concave portion formed bydenting the 1-2nd sub-layer toward a center thereof, the second stackstructure has a second concave portion formed by denting the 2-2ndsub-layer toward a center thereof, and the third stack structure has athird concave portion formed by denting the 3-2nd sub-layer toward acenter thereof.
 20. The display panel of claim 18, wherein the pixelelectrode has a structure, in which a layer having a material same as amaterial in the 3-1st sub-layer, a layer having a material same as amaterial in the 3-2nd sub-layer, and a layer having a material same as amaterial in the 3-3rd sub-layer are sequentially stacked.